Applicants will receive competition-related information electronically and be invited to meetings and discussion sessions.
The Radiance Technologies Innovation Bowl is an academic competition between schools and conferences affiliated with the Radiance Technologies Independence Bowl and is sponsored by both Radiance Technologies and the Radiance Technologies Independence Bowl Foundation. Affiliated schools compete for a single $25,000 Grand Prize by developing innovative approaches to a current research and development topic selected by Radiance Technologies (see “2023-24 Topic” tab for this year’s topic). Evaluation of submissions is a two-step process. Teams submit their initial ideas and approaches during Phase 1 to Radiance Technologies prior to the end of the fall term. From these submissions, scientists and researchers within Radiance Technologies pick three final teams, announced at half-time during the Radiance Technologies Independence Bowl. These teams then further develop their ideas in the spring semester, Phase 2, through prototypes, models and simulation or experimentation and present their findings in person to a panel of experts. From these live presentations, a winning team is selected and awarded the $25,000 grand prize.
Universities form teams consisting of faculty and students to compete in the Radiance Technologies Innovation Bowl. The number of team members and composition is up to the discretion of the team, but we expect only one faculty member per team. Multiple teams from the same university are permitted. Teams will sign up early in the fall semester, Phase 1, and will be given additional information concerning the competition, see the ‘’Schedule” tab. There will be opportunities for teams to discuss their ideas with Radiance Technologies Subject Matter Experts (SMEs) during this phase. The goal of this initial phase is for the teams to provide a proof of principal or proof of concept for their innovative idea and show that it will work and the benefit of the approach. Teams will conduct initial research and assessments of their approach and present Phase 1 results in a written report along with a plan of action, if selected, for the next phase. This information will be evaluated by Radiance SMEs who will select three teams to move to the next phase. Phase II will take place in the spring semester. The three teams will mature their approach and produce a prototype, a model and simulation or other means to demonstrate the operation of their innovation. Teams will send two members to Radiance Technologies for in-person, final presentations (expenses paid by Radiance Technologies. Note: Virtual presentations are also acceptable). From these presentations, a winner will be selected and the $25,000 Grand Prize awarded.
All efforts will be taken to schedule events so they do not conflict with school schedules concerning finals and graduation. See “Schedule.”
If you have questions, please feel free to contact us using at the email listed under the Contact tab.
Participation is open to all schools affiliated with the Radiance Technologies Independence Bowl. Team leads can be either faculty or student. It is up to the individual teams to decide on the number of team members, provided each team has no more than one faculty representative. Teams can sign up at any time after publication of the topic for the current school year, but they need to register online no later than September 27, 2023 to be able to participate in virtual meetings with Radiance SMEs. During these meetings, SMEs will be able to answer questions, interact with students, and provide information concerning report format, rules, and expectations. A roster of competitive teams will be published after the initial meeting.
Click the “Apply Here” button above. Applicants will receive competition-related information electronically and be invited to meetings and discussion sessions.
For general and special purpose processor to ‘optimize’ performance, design complexity increases as advancements in hardware acceleration require moving beyond monolithic integrated circuits. Heterogenous Packaging techniques, such as multi-chip modules and 2.5/3D ICs, provide an avenue for easily integrating multiple chips into a single packaged device with notable reductions in communication delay. By integrating multiple chips onto a shared substrate containing chip-to-chip interconnect such as interposers or Through-Silicon Vias (TSV), these techniques provide flexibility in integrating chips designed in various process nodes for further optimization in cost and performance. There are three areas of interest related to enabling or facilitating these advance packaging concepts that are can be pursued under this year’s Innovation Bowl. Specific topic areas of interest are listed below followed by a more detailed discussion of each area. Participating teams will be able to ask question and interact with Radiance Subject Matter Experts on this topic for further clarification.
Please address one of the following topics:
Topic #1: Novel hardware architectures for AI/ML systems enabled by Advanced Heterogeneous Packaging
Topic #2: Methods for fast thermal evaluations of 2.5 / 3D packaging assemblies to enable parametric testing of prototype configurations
Topic #3: Thermal solutions to enable tighter integration of chiplets in Advanced Packages
Artificial Intelligence/Machine Learning stands firmly as a rapidly-advancing field of study requiring and driving state-of-the-art design techniques and hardware architectures through need of specialized hardware accelerators. Initially, these improvements came in the form of domain-specific hardware such as Google’s Tensor Processing Unit [1] [4], IBM’s TrueNorth [2], and Intel’s Loihi [3]. However, as design complexity increases, advancements in hardware acceleration require moving beyond monolithic integrated circuits. Heterogenous Packaging techniques, such as multi-chip modules and 2.5/3D ICs, provide an avenue for easily integrating multiple chips into a single packaged device with notable reductions in communication delay. By integrating multiple chips onto a shared substrate containing chip-to-chip interconnect such as interposers or Through-Silicon Vias (TSV), these techniques provide flexibility in integrating chips designed in various process nodes for further optimization in cost and performance. Using these methodologies, novel architectures which reduce design complexity and cost of specialized accelerators while improving efficiency and yield will emerge. This Innovation Bowl topic involves the analysis and implementation of novel hardware architecture solutions utilizing advanced heterogenous packaging to create more efficient artificial intelligence and machine learning components.
[1] Jouppi, Norman P., et al. “In-datacenter performance analysis of a tensor processing unit.” Proceedings of the 44th annual international symposium on computer architecture. 2017.
[2] DeBole, Michael V., et al. “TrueNorth: Accelerating from zero to 64 million neurons in 10 years.” Computer 52.5 (2019): 20-29
[3] Orchard, Garrick, et al. “Efficient neuromorphic signal processing with loihi 2.” 2021 IEEE Workshop on Signal Processing Systems (SiPS). IEEE, 2021.
[4] Jouppi, Norm, et al. “Tpu v4: An optically reconfigurable supercomputer for machine learning with hardware support for embeddings.” Proceedings of the 50th Annual International Symposium on Computer Architecture. 2023.
Increasing computational requirements for Internet of Things (IoT), machine learning, and cloud computing applications cause challenges to the Moore’s Law technique of scaling semiconductor devices into smaller and more complex monolithic System-on-Chip (SoC) solutions. In advanced process nodes, standard 2D Integrated Circuits (ICs) for high-performance applications often have undesirable performance-per-watt metrics, as well as increased interconnect complexity, and interconnect delay. 2.5D and 3D integrated circuits, where multiple chips are integrated together into a shared module, present new design solutions to this problem. These systems have reduced interconnect power consumption and reduced signal delay, as well as the flexibility to use less costly semiconductor nodes for certain chips and more advanced nodes for others in the same system [1]. 2.5D technology involves side-by side integration of chips onto a shared substrate, with chips connected through bridge chip or interposer technologies [2]. 3D ICs involve vertically stacked and integrated ICs with direct connections up the hierarchy using either solder bumps or Through-Silicon Vias (TSVs). Tightly-integrating several high-performance chips onto a shared integrated substrate can create unwanted thermal stress on the system due to high power consumption in a small package. This thermal stress can cause mechanical or electrical failures in the design and is usually carefully mitigated in the design process. To reduce the overall cost of the 2.5D/3D system design, it is highly beneficial to characterize the thermal weaknesses and points of failure during the prototype stage through modeling and simulation. Power maps and thermal profiles of heterogeneously-integrated ICs can be created using multiphysics simulators and other advanced simulation and numerical methods [1] [2] [3]. This Innovation bowl topic involves the development of fast simulation techniques or fast numerical analyses to quickly evaluate the thermal characteristics of a 2.5D/3D IC to reduce the time-to-market and design cycle cost.
[1] K. Salah, “Survey on 3D-ICs thermal modeling, analysis, and management techniques,” 2017 IEEE 19th Electronics Packaging Technology Conference (EPTC), Singapore, 2017, pp. 1-4, doi: 10.1109/EPTC.2017.8277428.
[2] Y. Zhang, T. E. Sarvey and M. S. Bakir, “Thermal Evaluation of 2.5-D Integration Using Bridge-Chip Technology: Challenges and Opportunities,” in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 7, pp. 1101-1110, July 2017, doi: 10.1109/TCPMT.2017.2710042.
[3] M. Zhou, L. Li, F. Hou, G. He and J. Fan, “Thermal Modeling of a Chiplet-Based Packaging With a 2.5-D Through-Silicon Via Interposer,” in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 12, no. 6, pp. 956-963, June 2022, doi: 10.1109/TCPMT.2022.3174608.
Moore’s law has guided the continuous scaling of semiconductor devices to smaller and more complex process nodes. However, applications such as the Internet of Things (IoT), artificial intelligence and machine learning, as well as cloud computing applications require increasingly complex and costly Integrated Circuits (ICs) that simple transistor/process shrinking struggles to solve. Advanced packaging techniques, such as multi-chip-modules and 2.5/3D ICs, aim to present an alternative to process node shrinking by allowing for integration of multiple chips into a package with advanced interconnect techniques to allow for fast communication between components. Such techniques for 2.5D ICs include integrating chiplets onto a shared substrate with chip-to-chip connections through bridge chip technologies or interposer technologies [1]. Additional techniques can include solder bump or Through-Silicon Via (TSV) connections made between vertically-stacked chiplets to create a 3D IC. However, densely packing high-performance chiplet components into a small, advanced package causes high power consumption in a localized area. The resulting thermal stress can cause physical defects in semiconductor material, defects in solder bump material, unacceptable noise, or electrical failures on the system. As such, managing thermal effects for an efficient, tightly-integrated package is an area of utmost concern. Mitigation techniques often include heat sinks, heat spreaders, novel thermal interface materials (TIMs), liquid cooling, and thermally-driven design techniques earlier in the IC design cycle [2]. This Innovation Bowl topic involves the analysis and implementation of novel thermal management techniques to allow for tightly-integrated chiplets in efficient heterogeneous ICs.
[1] Y. Zhang, T. E. Sarvey and M. S. Bakir, “Thermal Evaluation of 2.5-D Integration Using Bridge-Chip Technology: Challenges and Opportunities,” in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 7, pp. 1101-1110, July 2017, doi: 10.1109/TCPMT.2017.2710042.
[2] K. Salah, “Survey on 3D-ICs thermal modeling, analysis, and management techniques,” 2017 IEEE 19th Electronics Packaging Technology Conference (EPTC), Singapore, 2017, pp. 1-4, doi: 10.1109/EPTC.2017.8277428.
Description of Contest:
Radiance Technologies, an Alabama based company located at 310 Bob Heath Drive, Huntsville, Alabama 35806 and the Independence Bowl Foundation, Inc. 401 Market Street, Shreveport, LA 71101 are jointly sponsoring an academic challenge (Innovation Bowl) for those schools affiliated with the Radiance Technologies Independence Bowl. The intention of the competition is to support engineering talent, create innovative solutions and approaches to real world problems and foster friendly academic competition across the schools associated with the Radiance Technologies Independence Bowl.
Standard format
Content
Evaluation
Final Report Format, Due March 27, 2024
Listed below are the format and desired requirements for the Phase 2 final report.
Same format as the Phase 1 report but with extended page count. It is expected that final report would be 5-7 pages not counting additional supporting information and references.
The overall objective of the Phase 2 report is to show the feasibility of your idea through an example. We would like to see how you can put the idea into practice. Real-world data is preferred but you can also use simulated data. While you are not strictly required to follow this format, we do need you to address the following items:
1. Introduction
2. Methodology
3. Execution
4. Results
5. Discussion
6. Conclusion and Recommendation
Geospatial Intelligence (GEOINT) is the information obtain for a particular geographical location through the exploitation of imagery and geospatial data. GEOINT uses overhead imagery from various Electro Optical/Infrared (EO/IR) sensors (images) combined with imagery analysis (determining what is in the image) and other geospatial data (characteristic reference information for the location, e.g. elevation, road and utility networks, vegetation, population, geodetic data, etc.). This combination provides the situational awareness of what is occurring or changing at a particular location. GEOINT is the combination and integration of a variety of multiple data sources. There is a plethora of open-source geospatial data repositories. Listed below are some of the available data sources but there are many others. For the Innovation Bowl competition, teams my use their own data and/or any of those listed below. There are also numerous commercial services that provide data for a fee. Radiance Technologies and the Independence Bowl Foundation do not provide funding for acquiring data and therefore it is up to the team to decide whether they want to incur any data cost. GEOINT is a combination of a lot of different data sources as can be seen from the list below. More information concerning data will be provided at the initial coordination meeting.
Competing against two other finalists – one team from the University of Alabama at Birmingham (UAB) and one from the University of Texas at San Antonio (UTSA), Team BHAM_CS from UAB took home the $25,000 grand prize for their first-place finish. Their submission, “Automating Flood Extent Mapping on Earth Imagery Using Elevation-Guided AI Technology,” was the winning project. Congratulations to student lead Saugat Adhikari, faculty lead Da Yan, and student team members Mirza Sami and Jalal Khalil.
Team BHAM_CS examined the problem of automating the mapping of the extent of flooding on earth imagery using Artificial Intelligence (AI) technology. Their approach rapidly and efficiently used satellite imagery of disaster areas and 3-D elevation mapping to determine the extent of flooding. They would segment the map and apply their AI approach to the separate segments to determine the susceptibility to flooding for the different segments of the image. This alleviates the problem of relying on elevation alone as the key to predicting flooding. They then refined the image using a graphical model with a hidden Markov tree. The result is an accurate prediction of the extent of flooding, which disaster management organizations can use to help guide their response.
